Agilent Technologies Introduces Industry’s First Reference Clock Multiplier for Receiver Test
New Solution Improves Accuracy and Simplifies Setup for Receiver Testing of PCI Express,
MIPI M-PHY and SD UHS-II
January 24, 2012
SANTA CLARA, Calif., Jan. 24, 2012 – Agilent Technologies Inc. (NYSE: A) today announced the industry’s first
reference clock multiplier. The Agilent N4880A reference clock multiplier enables R&D and test engineers to lock the pattern generator
clock of the
J-BERT N4903B and the
to reference clocks from the system under test.
The new solution supports multiple reference clock rates ranging from 19 to 100 MHz for receiver test applications such as PCIe® 1.x,
2.x and 3.0 main boards, MIPI M-PHY devices and UHS-II host devices. The use of the reference clock multiplier significantly simplifies
the receiver test setup, helping R&D and test teams to accurately characterize and verify standard compliance under easy to reproduce
With common reference clock architectures, where the host cannot run on an external reference clock,
it is necessary to lock the generated stressed-pattern signal to the reference clock from the receiver under test.
That’s because the receiver under test also derives its sampling clock from this reference clock. Not locking the stressed
pattern generator to the same reference clock would lead to wrong and non-reproducible jitter-tolerance test results.
Some emerging and existing standards require this test topology: the PCI Express® rev 2.x and 3.0 CEM specifications from
the PCI-SIG®, the MIPI M-PHY draft specification from the MIPI alliance, and the draft SD card specification for UHS-II host
devices use a common reference clock architecture. In the past it was very cumbersome to reproduce such setups and it was not
easy to reproduce stress conditions, especially when spread-spectrum clocking and low-frequency jitter components are present
on the reference clock signal.
Agilent’s N4880A reference clock multiplier provides a multiplying phase locked loop (PLL),
which enables users to lock the pattern generators of the J-BERT N4903B high-performance serial BERT
and the ParBERT 81250A to such a reference clock.
SSC and jitter are fed through the N4880A up to the PLL bandwidth.
At its reference clock input, the N4880A supports multiple clock rates: 100 MHz for PCIe 1.x, 2.x and 3.0 CEM test;
19.2 to 52 MHz for MIPI M-PHY gear 1, 2 and 3 devices; and 26 to 52 MHz for UHS-II host devices. The bandwidth of the
multiplying PLL automatically adapts. Users can control the settings of the N4880A from a stand-alone user interface
running on a Windows PC via a USB connection.
Benefits of the Agilent N4880A reference clock multiplier include:
• Precise and reproducible receiver tolerance testing by emulating real-world clock conditions.
This is achieved by transparency to low-frequency jitter and SSC profiles from the system under test,
its tolerance of huge amounts of SSC for UHS-II reference clocks and its low input sensitivity to handle very low voltage levels.
• Higher R&D efficiency enabled by reduced complexity of test setup.
• Investment protection enabled by supporting multiple reference clock rates ranging from 19 to 100 MHz and support for J-BERT
and ParBERT external clock mode, for PCIe 1.x, 2.x, and 3.0, SD card UHS-II, and MIPI M-PHY.
“Agilent’s new N4880A reference clock multiplier fills a critical need for R&D and test engineers who want to characterize and
release the next generation of PCI Express main boards, MIPI M-PHY chipsets and UHS-II host devices,” said Jürgen Beck,
general manager of Agilent’s Digital Photonic Test Division. “By adding our expertise in emulating stress signals and accurate
receiver characterization, we again confirm our commitment to enable R&D teams to efficiently release robust, next-generation devices
and boards for the server, mobile computing and storage industry.”
Agilent’s Digital Test Standards Program
Agilent’s solutions for digital applications are driven and supported by Agilent experts who are involved in various international
standards committees. Experts from the Agilent Digital Test Standards Program are active in the
Joint Electronic Devices Engineering Council,
Video Electronics Standards Association,
Serial ATA International Organization,
Serial Attached SCSI (T10),
Ethernet standards (IEEE 802.3),
Optical Internetworking Forum and many others.
Agilent’s involvement in these standards groups and their related workshops, plugfests, and seminars enable the company to bring the
right solutions to the market when its customers need them.
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